Among semiconductor device manufacturing processes, one of the most important processes is patterning and etching of a silicon oxide film, a silicon nitride film, a polysilicon film, a metal film, or any other film formed on the surface of a wafer into the desired shape. Wet etching, one of such etching techniques, has required a fine processing agent capable of selectively etching only an etching target film.
When a silicon oxide film is the target of etching, examples of such a fine processing agent include buffered hydrofluoric acid and hydrofluoric acid. However, when such buffered hydrofluoric acid or hydrofluoric acid is used as a fine processing agent in the processing of a laminated film composed of a silicon oxide film and a silicon nitride film, the silicon nitride film is also etched at the same time. As a result, patterning into the desired shape becomes difficult.
For example, a fine processing agent containing hydrofluoric acid and an anionic surfactant such as ammonium lauryl sulfate can solve such a problem and selectively etch only a silicon oxide film (see Patent Document 1 listed below). Unfortunately, such a fine processing agent has very high foaming ability and therefore is not suitable for use in semiconductor device manufacturing processes.
On the other hand, for example, a DRAM (Dynamic Random Access Memory) is a semiconductor device that is produced through wet etching with a fine processing agent. A DRAM cell includes one transistor and one capacitor. DRAM integration has increased about four times in the last three years. DRAM integration is generally achieved by integration of capacitors. Therefore, while the area occupied by a capacitor is reduced, an increase in capacitor area, a reduction in capacitor insulating film thickness, and incorporation of a high dielectric constant film are made so that the capacitance required for stable storage operation can be ensured.
A silicon oxide film has been used as the capacitor insulating film, and a reduction in the film thickness has been made. However, the reduction in the thickness of a silicon oxide film as a capacitor insulating film has reached a limit for 1 Mbit DRAM. In a 4 Mbit DRAM, therefore, a silicon nitride film is used as an insulating film. As integration has proceeded, a tantalum oxide film has also begun to be used.
A 64 Mbit generation DRAM has a cylindrical capacitor structure. The problem described below occurs when a conventional etchant is used in a process that includes forming cylindrical capacitor lower electrodes and then removing the formed silicon oxide film by wet etching to form a capacitor.
Specifically, after the capacitor lower electrodes are formed, the formed silicon oxide film is removed by wet etching, and rinsing with ultrapure water and drying are further performed. The drying process has the problem that due to the surface tension of water present between the capacitor lower electrodes, a “leaning” phenomenon, in which the lower electrodes lean and come into contact with each other, frequently occurs to induce 2-bit failure. Thus, Patent Document 2 listed below discloses a technique for forming a silicon nitride support film between capacitor lower electrodes. Patent Document 3 listed below also discloses a technique for forming a silicon nitride film as an insulating film for improving insulating properties from bit lines, and Patent Document 4 listed below also discloses a technique for forming a silicon nitride film as an etching stopper film for the subsequent process of etching a silicon oxide film.
In these semiconductor device manufacturing processes, the use of a conventional etchant has the problem that the silicon oxide film disclosed as a support film in Patent Document 1, the silicon nitride film disclosed in Patent Document 2, or the silicon oxide film disclosed as an etching stopper film in Patent Document 3 is also etched together with the etching target.